1. Field of the Invention
The present invention relates to a capacitor of a semiconductor device, and more particularly, to a metal insulator metal (MIM) capacitor of a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Generally, a capacitor is constructed with a bottom electrode, a dielectric layer, and a top electrode. The dielectric layer serves as an insulation layer. The capacitor stores data through charge accumulation. Capacitors are classified into a metal insulator metal (MIM) capacitor, a metal insulator silicon (MIS) capacitor, and a polysilicon insulator polysilicon (PIP) capacitor, depending on their structures.
A related art MIM capacitor will be described below with reference to FIG. 1.
Referring to FIG. 1, the related art MIM capacitor includes a bottom electrode 21 formed on a substrate 10, a dielectric layer 40 formed on the bottom electrode 21, and a top electrode 51 and 61 formed on the dielectric layer 40. Accordingly, the capacitor has an MIM structure. The top electrode may include a conductive plug 51 and a conductive layer 61.
Also, the related art MIM capacitor is formed together with a metal interconnection because it has to be simultaneously implemented with other semiconductor devices.
For this reason, a bottom interconnection 22 is formed on the substrate 10 together with the bottom electrode 21. After an interlayer insulation layer 30 is formed on the substrate 10, a via plug 52 is formed together with the conductive plug 51. Then, a top interconnection 62 is formed together with the conductive layer 61.
As the semiconductor device is integrated more highly and miniaturized, an area of a memory cell is getting smaller. However, a unit area of the capacitor cannot be reduced in proportion to the area reduction of the memory cell. This is because electric capacity per unit memory cell is required to have more than a predetermined value so as to maintain a stable operation of the semiconductor device.
Many attempts have been made to maintain the capacitor capacity to more than an appropriate value within a restricted memory cell area. Examples of these studies are a method of reducing a thickness of a dielectric layer, a method using material with high dielectric constant, a method of increasing an effective surface area of a capacitor, and so on.
However, the size of the memory cell is reduced with the high integration of the semiconductor device and thus the effective surface area of the capacitor is also reduced. Consequently, the related art has a problem in that an appropriate electric capacity cannot be obtained.
Also, there is a limitation in miniaturization of the semiconductor device because the size of the memory cell cannot be reduced for the purpose of the appropriate electric capacity of the capacitor.